Translation guide
A register in a CPU that holds the memory address of the next instruction to be executed. In Japanese computing contexts, this is typically referred to by its English-derived term or a direct translation.
The hardware register that stores the address of the next instruction to fetch and execute.
Standard Japanese term combining 命令 (instruction) and ポインタ (pointer) with レジスタ (register). Widely understood in technical manuals and computer architecture contexts.
命令ポインタレジスタは、次に実行する命令のアドレスを保持します。
The instruction pointer register holds the address of the next instruction to be executed.
In general computer science texts, プログラムカウンタ (program counter) is very common. When specifically discussing CPU registers in detail, 命令ポインタレジスタ or インストラクションポインタレジスタ may be preferred. In assembly language contexts, the abbreviated form (e.g., EIP, RIP) is often used directly.
Loanword version using インストラクション (instruction) instead of 命令. Common in texts that prefer English-derived terms.
x86アーキテクチャでは、インストラクションポインタレジスタはEIPと呼ばれます。
In the x86 architecture, the instruction pointer register is called EIP.
Often used interchangeably with instruction pointer, though technically 'program counter' may refer to the same concept. Very common in Japanese computing literature.
プログラムカウンタは命令ポインタレジスタと同義で使われることが多いです。
Program counter is often used synonymously with instruction pointer register.
Abbreviation using 'IP' (Instruction Pointer). Used in contexts where the register name is abbreviated, like in assembly language documentation.
IPレジスタの値をスタックにプッシュします。
Push the value of the IP register onto the stack.