noun
instruction fetch cycle
Technical term in computer architecture; refers to the stage in a CPU's instruction cycle where the next instruction is retrieved from memory.
命令取出し段階では、プログラムカウンタが指すアドレスから命令が読み出される。
In the instruction fetch cycle, the instruction is read from the address pointed to by the program counter.
Compound of 命令 (instruction), 取出し (fetching), and 段階 (stage/cycle). A straightforward technical term formed from standard computing vocabulary.