stuck-at fault
Technical term in digital circuit testing: a fault model where a signal line is permanently fixed at logic 0 or 1. 'Stack fault' is a less common variant gloss.
The stuck-at fault model is widely used in LSI testing.
General word for failure or breakdown; 縮退故障 is a specific fault model in electronics.
Compound of 縮退 (degeneracy, contraction) and 故障 (fault, failure). The term is a direct translation of the English 'stuck-at fault' used in digital circuit testing.