論ろん理り合ごう成せい

noun, noun or participle which takes 'suru'

logic synthesis

A semiconductor design technique where a high-level description of a circuit is automatically converted into a gate-level netlist. Used in electronic design automation (EDA).

• このツールはRTLからゲートレベルへの論ろん理り合ごう成せいを行おこないます。

  This tool performs logic synthesis from RTL to gate level.

• 論ろん理り合ごう成せいの結けっ果か、タイミング制せい約やくを満みたす回かい路ろが生せい成せいされた。

  As a result of logic synthesis, a circuit that meets timing constraints was generated.