layout-design exploitation right
A legal right under Japanese semiconductor law, allowing the holder to commercially exploit a registered circuit layout design.
The layout-design exploitation right is a right protected under the Act on the Circuit Layout of Semiconductor Integrated Circuits.
Refers to the circuit layout itself, while 回路配置利用権 is the legal right to exploit that layout.
The semiconductor integrated circuit whose layout design is protected by this right.
Compound of 回路配置 (circuit layout) + 利用 (exploitation) + 権 (right). A modern legal term coined under Japanese semiconductor legislation.